PTX instructions that cicc cannot generate
While reverse-engineering Nvidia's compilation pipeline, I extracted the set of PTX instructions that cicc (the CUDA C++ frontend) is capable of emitting. The next logical step is to intersect them with full set of instructions accepted by ptxas - so we could get instructions which cicc just unable to produce. To do this I add to iptx.pl new option -U and got file ptx_not_in_cicc.txt with 114 unique names
PTX in total has only 268 unique names - so 114 is 42.5%. Notable missing instructions include:
- cctl for cache control
- lop3 - yeah, I saw them many times in SASS, so it generated by ptxas during optimization passes
- r2p
- 11 variants of tcgen05.*
- mad24/mul24
- all video instructions like vadd/vmad/vset etc
This gap is large enough to be surprising and leads me to conclusion that official LLVM MLIR dialects for cuda are totally incomplete
MLIR was initially a very dubious idea IMHO - what if we have some unscrupulous HW vendor who prefers to hide many details of it's hardware? And even worse - when multiple MLIR dialects are involved (like gpu, nvgpu, nvvm, linalg etc), at least one of them has to maintain accurate mappings between all of them. This leads to exponential explosion of complexity - you can expect items from each of used dialects while doing optimization, and also creates surface area for bugs.